Training with MicroConsult 2026

Location: Face-to-face or onsite training (Germany), online training

Dates: On request

Content

PLS UDE Basics

• Debug session set-up
• PLS UDE GUI (user interface)
• Register and memory access: display, modification
• Debug process: start/stop/single-step, breakpoints
• Sample-based code profiling

High-level Language Debugging with the PLS UDE Debugger

• Loading an application (Flash programming)
• Displaying/ initializing/ changing variables
• Displaying stack/ call stack contents (stack/ call stack view)
• Monitoring variables at runtime

PLS UDE Script Language

• Generating script files
• Debugging script files

Multicore Debugging

• Debug session set-up for multicore (for two or more cores)

Location: Face-to-face or onsite training (Germany), online training

Dates:

• 14.07.2026, Live-Online Training
• On request

Content

• Tool Architecture
• Watching and Changing Registers
• Watch Window (Variables)
• Expressions
• Locals and Call Stack
• Memory Content
• Graphic Display
• Run Control
• Runtime Measurement
• Profiling
• Multicore Debugging (Load, Run, Break, Cache, MPU)
• Automation - Overview (e.g. Python)
• Trace Recording
• Configuration (Compact, Advanced)
• Trace-Based Profiling
• Data Trace
• Code Coverage
• Execution Sequences
• Call Graph
• GTM Debug/Trace
• Peripheral Trace

Location: Face-to-face or onsite training (Germany), online training

Dates:

• 20.07. – 24.07.2026 (5 days), face-to-Face Training
• Live-online training on request
• Onsite-training on request

Content

Introduction

System Architecture

Internal Infrastructure

• SRI
• FPI
• LLI

Virtual Machines and Hypervisor

TriCore™ CPU

• Context switching
• New instructions
• Virtualization
• Trap system
• MPU
• System timer

Protection Mechanisms

• PROT
• APU

Memory

• NVM
• UCBs
• SOTA
• Cache

Ports

Interrupt Router (IR)

System Direct Memory Access Controller

Safety Concept

• CRC engine
• Watchdogs
• BIST
• Clocking
• Voltage monitors
• SMU

Security Concept

• CS real-time module
• CS satellite

Power Management System

• Domains
• Wakeup timer
• RTC
• Standby controller

System Control and Management

• Clocking
• NMI
• Reset
• Firmware
• Boot

Complex Peripherals Overview and Special Features

• PPU
• GTM
• CAN
• xSPI
• PCIe
• ETH

Data Routing Engine

Analog to Digital Conversion

• TMADC
• Fast compare
• DSADC
• CDSP

Multicore Debug

Location: Face-to-face or onsite training (Germany), online training

Dates:

• 22.06. – 26.06.2026 (5 days), face-to-Face Training
• Live-online training on request
• Onsite-training on request

Content

Infineon AURIX™ 2G Architecture

• Multicore architectural blocks
• Interconnectivity
• Consequences for software architectures

CPU Subsystem

• Multicore instruction set extensions
• Registers files and context switching
• Memory protection unit (software monitoring)

Internal Connectivity

• Crossbar and peripheral bus
• CPU clustering
• Performance aspects for software

Memory

• Memory map
• Configuration options
• Cache and software handling
• Types
• Hierarchy
• Test

Infineon Low-Level Drivers: Overview

• Configuration structures
• Application programming interface
• Library distribution
• Frameworks and demos

Ports

Exceptions and Handling

• Traps (hardware and software)
• Interrupts (hardware and software)
• Vector tables
• Broadcast software interrupts (core synchronization)
• External interrupts

Direct Memory Access Controller DMA

• Move engines
• Triggering (hardware and software)
• Advanced features (software relaxation)

Timer

• System timer (STM)
• General purpose timer 12 (GPT12)
• Capture compare unit (CCU)
• Watchdog timer (WDT)
• Temporal protection timer (TPS, exception timer)
• Generic timer module (GTM) - overview

Safety and Security

• Safety measures
• Safety management unit (SMU)
• Protection mechanisms
• IO monitoring
• Hardware security module (HSM) - implementation overview

Multicore Aspects

• Startup and boot
• Low power options
• Communication and synchronization
• Intrinsics usage in C/C++
• Tool aspects (compiler, linker)
• Debugging (AMP, SMP)

System Control

• Reset: sources, types and consequences
• Boot: software configuration and modes
• Clocking
• Emergency stop requests

Power Management System (PMS)

• Supply generation options
• Embedded voltage regulators
• Standby and wakeup
• Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

• Micro second channel (MSC)
• Serial peripheral interface (QSPI)
• Inter IC interface (I2C)
• UART (ASCLIN)

Sensor Interfaces

• SENT
• PSI5
• PSI5-S

Analog To Digital Converter

• EVADC
• EDSADC
• Enhanced features offloading software

Automotive Interfaces: Overview

• LIN
• CAN
• FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview/Demo

Debug

• Interfaces
• Tracing
• Multicore aspects

Exercises

• Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.

Location: Face-to-face or onsite training (Germany), online training

Dates: On request

Content

Infineon AURIX™Architecture: Overview

AURIX™ Multicore

• CPU, pipelines, register sets, floating point unit FPU, DSP extension
• Memory model, local and global memory units
• On-chip bus systems: 64-bit XBAR, 32-bit system peripheral bus SPB
• TRAP handling

Ports (Pin Definition and Port Functions)

Protection System

Multicore Interrupt Processing: Interrupt Router

Direct Memory Access Controller DMA

On-Chip AURIX™ Peripherals

Timer

• System timer module STM
• Generic timer module GTM
• Capture and compare unit CCU6

Communication Interfaces

• UART/LIN, QSPI, I2C, MSC, HSSL & HSCT
• Overview: MultiCAN, Ethernet, FlexRay®

Sensor Interfaces

• Single edge nibble transmission SENT
• Peripheral sensor interface PSI5

Analog-to-Digital Converter

• Versatile analog-digital converter VADC
• Delta-sigma analog-digital converter DSADC

System Control Unit SCU

• Clock control
• Reset system
• Power management
• External request unit ERU
• Start-up process
• Watchdog timer WDT

Safety

On-chip Debug System OCDS

Overview: Emulation Device & Calibration

Exercises

• Exercises are performed with an Infneon AURIX™ board, covering the following aspects: interrupt controller, DMA controller, multicore start-up, initialization of peripherals.

Location: Face-to-face or onsite training (Germany), online training

Dates: On request

Content

Bosch Semiconductors Generic Timer Module GTM Architecture v1 and v3: Overview

GTM Module

• Clock time base module CTBM
• Clock management unit CMU
• Time base unit TBU
• Digital phase-locked loop DPLL
• Timer input mapping module MAP
• Advanced routing unit ARU
• Timer input module TIM
• Timer output module TOM
• ARU-connected TOM ATOM
• Parameter storage modules PSM (FIFO submodule)
• Broadcast module BRC
• Sensor pattern evaluation SPE
• Monitor unit MON
• Output compare unit CMP

GTM Functionality

• Timer / counter (free running / reset)
• Capture / compare
• Input signal filtering
• PWM signal measurement
• Duty cycle measurement
• Complex PWM signal generation
• Pulse count modulation PCM
• Global time and/or angle recognition
• Generation of complex angle clock
• BLDC support

GTM µC Interface

• AEI Mux
• Debug
• Interrupt concentrator ICM

Exercises

• This workshop implements hands-on exercises with an AURIX™ board, practicing the following aspects:
• TIM PWM measurement
• TOM PWM generation
• ATOM PWM generation
• MCS programming
• Host-core to GTM-communication

Location: Face-to-face or onsite training (Germany), online training

Dates:

• 18.06. – 19.06.2026 (2 days), face-to-Face Training
• Live-online training on request
• Onsite-training on request

Content

• Introduction
• Inside Hardware Security Module
• CPU Subsystem Overview
• System Aspects (Configuration, Boot, Reset, Debug)
• Bridge
• Timer Module and Watchdog
• True Random Number Generator

Location: Face-to-face or onsite training (Germany)

Dates:

• On request

Content

• Infineon XMC4000 Architecture: Overview
• XMC4000 Arm® Cortex™-M4, M3, M1, M0 Core: Overview
• Memory Units SRAM, Program Memory Unit (PMU), PFlash, BROM
• Interrupt und Exception Handling, NVIC
• Event Request Unit (ERU)
• Direct Memory Access Controller (DMA)
• CRC (FCE)
• System Control Unit (SCU), System Timer Module (STM), Window
• Watchdog Timer (WDT), Real-time Clock (RTC)
• DAvE® 4
• Ports
• Special Timers and PWM Units
• High-resolution PWM, POSIF
• ADC; Delta-Sigma ADC DSD, DAC
• Overview: USIC, UART, CAN, LIN, SPI, I2C, I2S
• Debug and Trace
• Overview: CMSIS
• Exercises
  • Exercises are performed with an XMC4000 starter kit, focusing on the aspects interrupt controller, DMA controller, basic peripheral modules.

Location: Face-to-face or onsite training (Germany)

Dates:

• On request

Content

Get to know the architecture of the Stellar automotive multicore microcontroller family

Location: Face-to-face or onsite training (Germany), online training

Dates:

• 01.07.-03.07.2026 (3 days), face-to-face training
• 18.02.-20.02.2026 (3 days), live online training
• Onsite training on request

Content

Multicore Microcontroller Architecture

• Definition of multicore architectures
• Homogeneous/heterogeneous multicore architectures with shared memory and/or non-shared memory
• Software aspects for multicore processing
• Core interfaces and memories: core-local cache and SPRAM (level 1 memory); global/shared SRAM (level 2 memory), snoop logic, cache coherency
• Requirements for instruction throughput (MIPS)
• Core synchronization
• Co-processor functionality
• New core bus systems (crossbar)
• Semaphores: memory resource access control
• Memory protection (access protection)
• Multicore interrupt processing
• Multicore start-up/initialization: boot process, set-up of primary and secondary CPU(s)
• Debug interface(s)

Multicore Microcontroller Tool Aspects

• C/C++ compiler: extensions for multicore
• Locating program and data sections in specific memory areas/segments; control of access rights to global/external definitions
• Locator safety support: variable access control for multicore modules

RTOS

• Multicore aspects for RTOS software
• Scheduler: software/task deployment and execution strategies
• Partitioning
• Task synchronization concepts
• Task communication concepts
• Programming models and multicore API: communication, resource management
• Examples of multicore RTOS implementations

Multicore Debugging and Test Aspects

• Debugger extensions for multicore: core synchronization during debugging, synchronous start/stop, multicore breakpoint handling, core context sensitive visualization
• Performance and timing analysis, analysis of software runtime behaviour (profiling)
• Multicore and trace handling

Safety

• Multicore in standards
• Hardware safety measures
• Safety management unit SMU
• Bus error detection and protection mechanisms
• Safety core (checker core, lockstep core)
• Safety on-chip test features

Practical Exercises - Performed on an Evaluation Board based on Aurix Microcontrollers

• Multicore start-up behavior
• Memory allocation and partitioning
• Decomposition of existing singlecore applications
• Porting to multicore
• Synchronization/communication
• Protection mechanisms
• Performance measurement

Location: Face-to-face or onsite training (Germany)

Dates: On request

Content

Infineon TriCore™ Architecture: Overview

TriCore™ Core Version V1.6

• CPU, pipelines, register sets
• Memory model, local memory units
• DSP support
• On-chip bus systems

TriCore™ Ports (Pin Definition and Port Functions)

Protection System

Interrupt System

TRAP System

Peripheral Control Processor PCP2

Direct Memory Access Controller DMA

TriCore™ Peripherals, AUDO MAX Family (TC1798/93/91/84/82/28/24)

Serial Interfaces

• Asynchronous serial interface ASCx
• Synchronous serial interface SSCx
• Micro second channel MSCx
• Micro link interface MLI
• MultiCAN
• FlexRay™

Timer

• System timer STM
• General purpose timer arrays GPTA
• Capture compare unit CCU

Analog-to-Digital Converter ADCx

Fast Analog-to-Digital Converter FADC

Sensor Interface SENT

External Bus Unit EBU (TC1793, TC1798)

System Control Unit SCU, Reset, Power Management

• Start-up process
• Resets (power-on, HW, SW, WDT, deep sleep reset)
• Clock control, PLL
• Power management
• Watchdog timer WDT

Device Initialization with DAvE

Debug Support (OCDS) and Environment Tools: Overview

Practical Exercises

• Initialization of periphery, interrupt handling, DMA application and PCP programming

Location: Face-to-face or onsite training (Germany)

Dates: On request

Content

Infineon TriCore™ Architecture: Overview

TriCore™ Core Version V1.3.1

• CPU, pipelines, register sets
• Memory model, local memory units
• DSP support
• On-chip bus systems

TriCore™ Ports (Pin Definition and Port Functions)

Protection System

Interrupt System

TRAP System

Peripheral Control Processor PCP2

Direct Memory Access Controller DMA

TriCore™ Peripherals, AUDO FUTURE Family (TC1797/67/36)

Serial Interfaces

• Asynchronous serial interface ASCx
• Synchronous serial interface SSCx
• Micro second channel MSCx
• Micro link interface MLI
• MultiCAN
• FlexRay™

Timer

• System timer STM
• General purpose timer arrays GPTA

Analog-to-Digital Converter ADCx

Fast Analog-to-Digital Converter FADC

External Bus Unit EBU (TC1797)

System Control Unit SCU, Reset, Power Management

• Start-up process
• Resets (power-on, HW, SW, WDT, deep sleep reset)
• Clock control, PLL
• Power management
• Watchdog timer WDT

Device Initialization with DAvE

Debug Support (OCDS) and Environment Tools: Overview

Practical Exercises

• Initialization of periphery, interrupt handling, DMA application and PCP programming

Location: Face-to-face or onsite training (Germany)

Dates: On request

Content

Infineon XC2000/XE16x/XC16x Architecture: Overview

XC2000/XE16x/XC16x and ST10: C166s V2 Core

• CPU, pipelines, register set, context switch, CPU special function register
• Instruction fetch unit and program flow control
• Memory architecture and address map
• Internal memory block (on-chip: program and data SRAMs, embedded flash)
• System and user stack
• Overview: Instruction set, special instructions and DSP support

Differences in Architecture: XE16x/XC22xx and XC16x

Ports (Pin Definition and Port Functions)

Hardware-near C with Keil/Tasking Tools

• C statements and their execution in Assembler
• Architecture-specific data types, global data handling

Programming Techniques

• Description of peripherals
• Layer model for embedded software systems

Driver Programming

• Structured driver model
• Low-level driver LLD

Interrupt, PEC and TRAP Handling

• Interrupt controller, vector table, prioritization
• Peripheral event controller PEC
• TRAPs (exception handling)

Serial Interfaces

• XC16x: asynchronous serial interface ASCx, synchronous serial interface SSCx
• XC2000/XE16x: universal serial interface channel modules USICx with the features ASC, SCI, LIN, SSC, SPI, IIC, etc.

General Purpose Timer Unit, Watchdog Timer WDT, Real Time Clock RTC

Overview: MultiCAN, Analog Digital Converter ADCx

Overview: Capture Compare Units (CC2, CCU6x)

System Control Unit, Reset, Clock, Power Management

• Start-up process
• Resets, power management
• Clock control, PLL
• External request unit ERU

Device Initialization with Digital Application virtual Engineer DAvE®

On-Chip Debug System (OCDS/JTAG) and Environment Tools: Overview

Exercises: For practical training, participants can chooseKeil C166/ µVision 4 or the Tasking Viper toolset.

The following exercises will be carried out in addition to the training content:

• Set-up of a new project: from device selection to debugger set-up
• Interrupt handling: interrupt vector table entry and interrupt service routine
• DMA transfer (using the PEC controller) in the context of serial communication
• Typed memory reservation - hardware-near C programming
• Use of power saving mechanisms like CPU IDLE mode
• Use of complex and time-critical peripherals: ADC with PEC/interrupt handling

Location: Face-to-face or onsite training (Germany)

Dates: On request

Content

• Overview of the STM32 Architecture (STM32F0, STM32F1, STM32F2, STM32F3 and STM32F4 series) for Arm Cortex®-M0, Arm Cortex®-M3 and Arm Cortex®-M4 processors
• CPU, Registers
• Internal Bus Architecture
• Stack Handling
• Memory Mapping and Boot Modes
• System Architecture
• On-Chip Flash Architecture
• Direct Memory Access Controller DMA
• Power Supply, Clock Control, Reset
• Power Management, Power Saving Modes
• Real-Time Clock RTC
• Window Watchdog WWDG, Independent Watchdog
• Port Architecture: GPIO/AFIO
• External Interrupt/Event Controller EXTI
• Analog-to-Digital Converter ADC
• Advanced Control and General Purpose Timers
• Serial Peripheral Interface SPI
• Inter Integrated Circuit IIC
• Universal Synchr. Asynchr. Receiver Transmitter USART
• Controller Area Network bxCAN
• STM32F10x Driver Library and Low-Llevel-Driver STM32 Cube

Ort: Präsenz- oder Onsite-Training (Deutschland), Online-Training

Termine: auf Anfrage

Inhalte

PLS UDE Grundlagen

• Debug Session Set-up
• PLS UDE GUI (Bedienoberfläche)
• Register- und Memory-Zugriffe anzeigen und ändern
• Debug-Prozess: Start/Stop/Single-Step, Break-Points
• Sample-based Code Profiling

High-level Language Debugging mit dem PLS UDE Debugger

• Applikation laden (Flash-Programmierung)
• Variable anzeigen, initialisieren, ändern
• Stack/Call-Stack-Inhalt anzeigen (Stack/Call Stack View)
• Variablen zur Programmlaufzeit überwachen

PLS UDE Skriptsprache

• Script File erstellen
• Script File debuggen

Multicore Debugging

• Debug-Session-Setup für Multicore (für zwei oder mehrere Cores)

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine:

• 14.07.2026, Live-Online Training
• Auf Anfrage

Inhalte

• Tool-Architektur
• Betrachten und Ändern von Registern
• Das Watch-Fenster (Variablen)
• Expressions
• Locals und Call Stack
• Speicherinhalte
• Grafische Darstellungen
• Run Control
• Laufzeitmessung
• Profiling
• Multicore-Debugging (Load, Run, Break, Cache, MPU)
• Überblick Automation (z.B. Python)
• Trace-Aufzeichnungen
• Konfiguration (Compact, Advanced)
• Profiling Trace-basierend
• Data Trace
• Code Coverage
• Execution Sequences
• Call Graph
• GTM Debug/Trace
• Peripheral Trace

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine:

• 20.07. – 24.07.2026 (5 Tage), Präsenz-Training
• 28.09. – 02.10.2026 (5 Tage), Live-Online-Training
• Onsite-Training auf Anfrage

Inhalte

Introduction

System Architecture

Internal Infrastructure

• SRI
• FPI
• LLI

Virtual Machines and Hypervisor

TriCore™ CPU

• Context Switching
• New Instructions
• Virtualization
• Trap System
• MPU
• System Timer

Protection Mechanisms

• PROT
• APU

Memory

• NVM
• UCBs
• SOTA
• Cache

Ports

Interrupt Router (IR)

System Direct Memory Access Controller

Safety Concept

• CRC Engine
• Watchdogs
• BIST
• Clocking
• Voltage monitors
• SMU

Security Concept

• CS Real-time module
• CS Satellite

Power Management System

• Domains
• Wakeup timer
• RTC
• Standby Controller

System Control and Management

• Clocking
• NMI
• Reset
• Firmware
• Boot

Complex Peripherals Overview and Special Features

• PPU
• GTM
• CAN
• xSPI
• PCIe
• ETH

Data Routing Engine

Analog to Digital Conversion

• TMADC
• Fast Compare
• DSADC
• CDSP

Multicore Debug

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine:

• https://admin.pls-mc.com/cms/pages/116/edit/#block-e2df969d-bb76-4951-be7f-56769fa823b2-section

Inhalte

Infineon AURIX™ 2G Architecture

• Multicore architectural blocks
• Interconnectivity
• Consequences for software architectures

CPU Subsystem

• Multicore instruction set extensions
• Registers files and context switching
• Memory Protection Unit (software monitoring)

Internal Connectivity

• Crossbar and peripheral bus
• CPU clustering
• Performance aspects for software

Memory

• Memory map
• Configuration options
• Cache and software handling
• Types
• Hierarchy
• Test

Infineon Low-Level Drivers: Overview

• Configuration structures
• Application programming interface
• Library distribution
• Frameworks and demos

Ports

• General purpose IO
• Alternate connections (multiplexing)
• Pin mapping

Exceptions and Handling

• Traps (hardware and software)
• Interrupts (hardware and software)
• Vector tables
• Broadcast software interrupts (core synchronization)
• External interrupts

Direct Memory Access Controller DMA

• Move engines
• Triggering (hardware and software)
• Advanced features (software relaxation)

Timer

• System Timer (STM)
• General Purpose Timer 12 (GPT12)
• Capture Compare Unit (CCU)
• Watchdog Timer (WDT)
• Temporal Protection Timer (TPS, Exception Timer)
• Generic Timer Module (GTM): Overview

Safety and Security

• Safety measures
• Safety Management Unit (SMU)
• Protection mechanisms
• IO monitoring
• Hardware security module (HSM): implementation overview

Multicore Aspects

• Startup and boot
• Low power options
• Communication and synchronization
• Intrinsics usage in C/C++
• Tool aspects (compiler, linker)
• Debugging (AMP, SMP)

System Control

• Reset: sources, types and consequences
• Boot: software configuration and modes
• Clocking
• Emergency stop requests

Power Management System (PMS)

• Supply generation options
• Embedded voltage regulators
• Standby and wakeup
• Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

• Micro Second Channel (MSC)
• Serial Peripheral Interface (QSPI)
• Inter IC Interface (I2C)
• UART (ASCLIN)

Sensor Interfaces

• SENT
• PSI5
• PSI5-S

Analog To Digital Converter

• EVADC: SAR conversion
• EDSADC: Delta-sigma conversion
• Enhanced features offloading software

Automotive Interfaces: Overview

• LIN
• CAN
• FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview

Debug

• Interfaces
• Tracing
• Multicore aspects

Übungen

• Es werden zahlreiche Übungen mit einem Infineon AURIX™ Board durchgeführt. Dabei kommen u.a. folgende Aspekte zur Anwendung: Einsatz von Low-Level-Treibern, Schutzmechanismen, Interrupt Controller, DMA-Controller, System-Timer, Port, Multicore-Aspekte, Monitoring, Performance-Messungen uvm.

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine: Auf Anfrage

Inhalte

Infineon AURIX™ Architektur: Überblick

AURIX™ Multicore

• CPU, Pipelines, Register Sets, Floating Point Unit FPU, DSP-Erweiterung
• Memory Model, Local und Global Memory Units
• On-chip-Bussysteme: 64-Bit XBAR, 32-Bit System Peripheral Bus SPB
• TRAP Handling

Ports (Pin-Definition und Port-Funktionen)

Protection System

Multicore Interrupt Processing: Interrupt Router

Direct Memory Access Controller DMA

On-Chip AURIX™ Peripherals

Timer

• System Timer Module STM
• Generic Timer Module GTM - Short Overview
• Capture and Compare Unit CCU6

Communication Interfaces

• UART/LIN, QSPI, I2C, MSC, HSSL & HSCT
• Überblick: MultiCAN, Ethernet, FlexRay®

Sensor Interfaces

• Single Edge Nibble Transmission SENT
• Peripheral Sensor Interface PSI5

Analog-Digital Converter

• Versatile Analog-Digital Converter VADC
• Delta-Sigma Analog-Digital Converter DSADC

System Control Unit SCU

• Clock Control
• Reset System
• Power Management
• External Request Unit ERU
• Start-up Prozess
• Watchdog Timer WDT

Safety

On-Chip Debug System OCDS

Überblick: Emulation Device & Calibration

Übungen

• Es werden Übungen mit einem Infineon AURIX™ Board durchgeführt. Dabei kommen folgende Aspekte zur Anwendung: Interrupt Controller, DMA-Controller, Multicore-Startup, Peripherie-Initialisierung

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine: Auf Anfrage

Inhalte

Bosch Semiconductors Generic Timer Module GTM Architektur v1 und v3: Überblick

GTM-Module

• Clock Time Base Module CTBU
• Clock Management Unit CMU
• Time Base Unit TBU
• Digital Phase Locked Loop (DPLL)
• Timer Input Mapping Module MAP
• Advanced Routing Unit ARU
• Timer Input Module TIM
• Timer Output Module TOM
• ARU-connected TOM ATOM
• Parameter Storage Modules PSM (FIFO Submodule)
• Broadcast Module BRC
• Sensor Pattern Evaluation (SPE)
• Multichannel Sequencer MCS
• Monitor Unit MON
• Output Compare Unit CMP

GTM-Funktionalität

• Timer/Counter (free running / reset)
• Capture / Compare
• Eingangssignal-Filterung
• PWM-Signalerfassung
• Duty Cycle Messung
• Komplexe PWM-Signalerzeugung
• Pulse Count Modulation PCM
• Globale Zeit- und/oder Winkelerfassung
• Erzeugung von komplexen Winkeltakten
• BLDC-Support

GTM µC Interfaces

• AEI Mux
• Debug
• Interrupt Concentrator ICM

Übungen

• Es werden Übungen mit einem Infineon AURIX™ Board durchgeführt. Dabei kommen folgende Aspekte zur Anwendung:
• TIM-PWM-Messungen
• TOM-PWM-Generierung
• ATOM-PWM-Generierung
• Komplexe PWM-Generierung
• Multi-Channel Sequencer
• DPLL

Ort: Präsenz- oder Onsite-Training (Deutschland), Live-Online-Training

Termine:

• 18.06. – 19.06.2026 (2 Tage), Präsenz-Training
• 17.09. – 18.06.2026 (2 Tage), Präsenz-Training
• Live-Online-Training auf Anfrage
• Onsite-Training auf Anfrage

Inhalte

• Introduction
• Inside Hardware Security Module
• CPU Subsystem Overview
• System Aspects (Configuration, Boot, Reset, Debug)
• Bridge
• Timer Module and Watchdog
• True Random Number Generator
• Hash Module
• Advanced Encryption Standard - 128 Bit (AES-128)
• Public Key Cryptography (PKC) Module

Ort: Präsenz- oder Onsite-Training (Deutschland)

Termine: Auf Anfrage

Inhalte

Kurze Einführung in die TriCore™-Architektur

Anwendungsbeispiel in C

• Fast Fourier Transformation FFT

TriCore™ Assembler Instruction Set

• Advanced SIMD Extension
• Vector Operations

Implementierung des Programmes als:

• Inline-/Embedded-Assembler
• Intrinsic-Funktionen
• Assembler-Routinen

Programmoptimierung

• Optimierung auf C-Ebene
• Optimierung auf Assembler-Ebene mit SIMD-Instructions
• Schleifenoptimierung, Vektorisierung

Performance-Analyse

• Profiling, Hotspots finden
• Hardware-Optimierung
• Cache-Optimierung
• Multiprozessor-Optimierung
• pthread, openMP oder 3 individuelle Main-Funktionen

Floating-Point Extension

• Floating Point Unit Instructions

MicroConsult Plus: Übungen auf einer Zielhardware

• Die Programme werden mit einem Eclipse GNU Tool-Plugin und auf einer TriCore™ basierenden Hardware ausgeführt und getestet (Infineon TC1797, TC1798, TC275).
• Für Onsite-Trainings werden die eingesetzten Tools und die Hardware-Plattform mit dem Kunden individuell abgestimmt.

Ort: Präsenz-Training (Deutschland), Online-Training

Termine: Auf Anfrage

Inhalte

• Infineon XMC4000 Architektur: Überblick
• XMC4000 ARrm® Cortex™-M4, M3, M1, M0 Core: Überblick
• Memory Units SRAM, Program Memory Unit (PMU), PFlash, BROM
• Interrupt und Exception Handling, NVIC
• Event Request Unit (ERU)
• Direct Memory Access Controller (DMA)
• CRC (FCE)
• System Control Unit (SCU), System Timer Module (STM), Window Watchdog Timer (WDT), Real-time Clock (RTC)
• DAvE® 4
• Ports
• Spezial-Timer und PWM-Units
• High-resolution PWM, POSIF
• ADC; Delta-Sigma ADC DSD, DAC
• Überblick: USIC, UART, CAN, LIN, SPI, I2C, I2S
• Debug und Trace
• Überblick: CMSIS
• Übungen
  • Es werden Übungen mit einem XMC4000 Starter-Kit durchgeführt. Dabei kommen folgende Aspekte zu Anwendung: Interrupt Controller, DMA Controller, Basis-Peripheriemodule

Ort: Präsenz- oder Onsite-Training (Deutschland)

Termine: Auf Anfrage

Inhalte

• Lernen Sie die Stellar Multicore-Mikrocontroller-Familie für den Automotive-Bereich kennen.

Ort: Präsenz- oder Onsite-Training (Deutschland), Online-Training

Termine:

• 01.07-03.07.2026 (3 Tage), Präsenz-Training
• 18.02.-20.02.2026 (3 Tage), Libe-Online-Training
• Onsite-Training auf Anfrage

Inhalte

Multicore-Mikrocontroller-Architektur

• Begriffsklärung von Multicore-Architekturen
• Homogene / heterogene Multicore-Architekturen mit shared Memory und/oder non-shared Memory
• Software-Aspekte für die Multicore-Verarbeitung
• Core-Interfaces und Memories: Core-local Cache und SPRAM (Level 1 Memory), Global/Shared SRAM (Level 2 Memory), Snoop-Logik (Cache-Kohärenz)
• Anforderungen an den Befehlsdurchsatz (MIPS)
• Core-Synchronisation
• Coprozessor-Funktionalität
• Neue Core-Bussysteme (Crossbar)
• Semaphore: Speicher-Zugriffssteuerung
• Speicherschutz (Zugriffschutz)
• Multicore Interrupt-Verarbeitung
• Multicore Start-up und Initialisierung: Boot-Prozess, Set-up von primären und sekundären CPUs
• Debug-Interface(s)

Multicore-Mikrocontroller Tool-Aspekte

• C/C++ Compiler: Erweiterungen für Multicore
• Lokatieren von Programm- und Datensections in spezifische Speicherbereiche, Steuerung der Zugriffsrechte für Global-/Extern-Definitionen
• Locator Safety Support: Variablen-Zugriffssteuerung für Multicore-Module

RTOS

• Multicore-Aspekte für RTOS-Software
• Scheduler: Softwareverteilungs- und -ausführungsstrategien
• Partitionierung
• Synchronisationskonzepte
• Kommunikationskonzepte
• Programmiermodelle und Multicore API: Kommunikation, Ressourcen-Management
• Beispiele für Multicore-unterstützende RTOS-Implementierungen

Multicore-Debugging und -Testaspekte

• Debugger-Erweiterungen für Multicore: Core-Synchronisation beim Debuggen, synchroner Start/Stop, Multicore Breakpoint Handling, Core-Context sensitive Darstellungen
• Performance- und Timing- Analyse, Analyse des Laufzeitverhaltens von Software (Profiling)
• Multicore und Trace-Aufzeichnungen

Safety

• Multicore in den Normen
• Hardware Safety Measures
• Safety Management Unit SMU
• Bus Error Detection und Protection Mechanismen
• Safety Core (Checker Core, Lockstep Core)
• Safety on-Chip Testfeatures

Übungen: Werden auf Evaluierungsboards basierend auf Aurix-Mikrocontrollern durchgeführt

• Multicore-Startverhalten
• Speicher-Allokation und -Partitionierung
• Dekomposition von bestehenden Singlecore-Applikationen
• Portierung auf Multicore
• Synchronisation/Kommunikation
• Schutzmechanismen
• Performance-Messungen

Ort: Präsenz- oder Onsite-Training (Deutschland), Online-Training

Termine: Auf Anfrage

Inhalte

Infineon TriCore™ Architektur: Überblick

TriCore™ Core Version V1.6

• CPU, Pipelines, Register Sets, MPU, FPU
• Memory Model, Local Memory Units
• DSP Support
• On-Chip Bussysteme

TriCore™ Ports (Pin-Definition und Portfunktionen)

Protection System

Interrupt-System

TRAP-System

Peripheral Control Processor PCP2

Direct Memory Access Controller DMA

TriCore™ Peripherie, AUDO MAX (TC1798/93/91/84/82/28/24)

Serielle Schnittstellen

• Asynchronous Serial Interface ASCx
• Synchronous Serial Interface SSCx
• Micro Second Channel MSCx
• Micro Link Interface MLI
• MultiCAN
• FlexRay™

Timer

• System Timer STM
• General Purpose Timer Arrays GPTA
• Capture Compare Unit CCU

Analog-to-Digital Converter ADCx

Fast Analog-to-Digital Converter FADC

Sensor Interface SENT

External Bus Unit EBU (TC1793, TC1798)

System Control Unit SCU, Reset, Power Management

• Start-up Prozess
• Resets (Power-on-, HW-, SW-, WDT-, Deep-Sleep Reset)
• Clock Control, PLL
• Power Management
• Watchdog Timer WDT

Bausteininitialisierung mit DAvE®

Debug Support (OCDS) und Environment Tools: Überblick

Praxisübungen

• Übungen zu Peripherie-Initialisierung, Interrupt-Handling, DMA-Anwendung und PCP-Programmierung

Ort: Präsenz- oder Onsite-Training (Deutschland)

Termine: Auf Anfrage

Inhalte

Infineon TriCore™ Architektur: Überblick

TriCore™ Core Version V1.3.1

• CPU, Pipelines, Register Sets, MPU, FPU
• Memory Model, Local Memory Units
• DSP Support
• On-Chip Bussysteme

TriCore™ Ports (Pin-Definition und Portfunktionen)

Protection System

Interrupt-System

TRAP-System

Peripheral Control Processor PCP2

Direct Memory Access Controller DMA

TriCore™ Peripherie, AUDO FUTURE (TC1797/67/36)

Serielle Schnittstellen

• Asynchronous Serial Interface ASCx
• Synchronous Serial Interface SSCx
• Micro Second Channel MSCx
• Micro Link Interface MLI
• MultiCAN
• FlexRay™

Timer

• System Timer STM
• General Purpose Timer Arrays GPTA

Analog-to-Digital Converter ADCx

Fast Analog-to-Digital Converter FADC

External Bus Unit EBU (TC1797)

System Control Unit SCU, Reset, Power Management

• Start-up Prozess
• Resets (Power-on-, HW-, SW-, WDT-, Deep-Sleep Reset)
• Clock Control, PLL
• Power Management
• Watchdog Timer WDT

Bausteininitialisierung mit DAvE®

Debug Support (OCDS) und Environment Tools: Überblick

Praxisübungen

• Übungen zu Peripherie-Initialisierung, Interrupt-Handling, DMA-Anwendung und PCP-Programmierung

Ort: Präsenz- oder Onsite-Training (Deutschland)

Termine: Auf Anfrage

Inhalte

Infineon XC2000/XE16x/ XC16x Architektur: Überblick

XC2000/XE16x/ XC16x und ST10: C166S V2 Core

• CPU, Pipeline, Register Set, Context Switch, CPU Special Function Register
• Instruction Fetch Unit und Program Flow Control
• Speicherarchitektur und Address Map
• Internal Memory Block (On-Chip: Program und Data SRAMs, Embedded Flash)
• System und User Stack
• Überblick Instruction Set, Spezialbefehle und DSP-Support

Architektur-Unterschiede XE16x/XC22xx und XC16x

Ports (Pin-Definition und Portfunktionen)

Hardwarenahes C mit Keil-/Tasking-Tools

• C-Statements und deren Ausführung in Assembler
• Architekturspezifische Datentypen, globales Datenhandling

Programmiertechniken

• Beschreibung von Peripherie
• Schichtenmodell für Embedded Softwaresysteme

Treiberprogrammierung

• Strukturiertes Treibermodell
• Low-Level Treiber LLD

Interrupt-, PEC- und Trap-Handling

• Interrupt Controller, Vektor-Tabelle, Priorisierung
• Peripheral Event Controller PEC
• TRAPs (Exception Handling)

Serielle Schnittstellen

• XC16x: Asynchrone serielle Schnittstelle ASCx / synchrone serielle Schnittstelle SSCx
• XC2000/XE16x: Universal Serial Interface Channel Modules USICx mit den Funktionen ASC, SCI, LIN, SSC, SPI, IIC, etc.

General Purpose Timer Unit, Watchdog Timer WDT, Real Time Clock RTC

Überblick: MultiCAN, Analog Digital Converter ADCx

Überblick: Capture Compare Units (CC2, CCU6x)

System Control Unit, Reset, Clock, Power Management

• Start-up Prozess
• Resets, Power Management
• Clock Control, PLL
• External Request Unit ERU

Bausteininitialisierung mit dem Digital Application virtual Engineer DAvE®

On-Chip Debug System (OCDS/JTAG) und Environment Tools: Überblick

Für die Übungen kann zwischen den Toolpaketen Keil C166/ Vision 4 und Tasking-Viper Toolset ausgewählt werden.

Folgende Übungen werden zu den einzelnen Themen durchgeführt:

• Setup eines neuen Projektes: von der Baustein-Auswahl bis hin zum Debugger-Setup
• Interrupt Handling: Interrupt-Vektortabelleneintrag und Interrupt-Serviceroutine
• DMA-ähnlicher Transfer mit dem PEC-Controller in Verbindung mit serieller Kommunikation
• Typisierte Speicherreservierung - hardwarenahe C-Programmierung
• Verwendung von Power-Saving Mechanismen wie CPU IDLE-Mode
• Einsatz von komplexen und zeitkritischen Peripherals: ADC mit PEC/Interrupt-Handling

Ort: Präsenz- oder Onsite-Training (Deutschland), Online-Training

Termine:

• 16.03.-18.03.2026 (3 Tage), Präsenz-Training
• 13.07.-15.07.2026 (3 tage), Live-Online-Training
• Onsite-Training auf Anfrage

Inhalte

• Überblick über die Architektur der STM32-Familie (STM32F0-, STM32F1-, STM32F2-, STM32F3- und STM32F4-Serie) für Arm Cortex®-M0, Arm Cortex®-M3 und Arm Cortex®-M4 Bausteine
• CPU, Register
• Interne Bus-Architektur
• Stack Handling
• Memory Mapping und Boot Modes
• System-Architektur
• On-Chip Flash-Architektur
• Direct Memory Access DMA
• Power Supply, Clock Control, Reset
• Power Management, Power Saving Modes
• Real-Time Clock RTC
• Window Watchdog WWDG, Independent Watchdog
• Port Architektur: GPIO/AFIO
• External Interrupt/Event Controller EXTI
• Analog-to-Digital Converter ADC
• Advanced Control and General Purpose Timers
• Serial Peripheral Interface SPI
• Inter Integrated Circuit IIC
• Universal Synchr. Asynchr. Receiver Transmitter USART
• Controller Area Network bxCAN
• STM32 Treiber-Bibliothek und Low-Level -Treiber STM32 Cube